[W-HU-71] Notes on Performance Evaluation and Hardware Selection of JMAG Parallel Solver

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1. Introduction

Lead times for the competitive design of automobiles and electric appliances are getting shorter and more unforgiving each year. One way to reduce design lead time is to incorporate Computer Aided Engineering (CAE). In particular, CAE related to electromagnetism often uses finite element analysis (FEA) [1] [2], and reduction of analysis time is in great demand with users.
One good solution is to increase speed using parallel processing [3] [4]. Hardware configurations influence software algorithms and affect parallel performance greatly, and hardware advances in recent years have been remarkable. This means that software algorithms also need to advance to keep up. At JMAG, we implement algorithms that are best suited for the latest hardware, and we produce some of the highest levels of parallel performance in the industry [5] [6]. In particular, the shared memory type parallel (SMP) solver described below is greatly improved in version 16.1, and the distributed memory type massively parallel (MPP) solver is vastly improved in version 17.0.
In this white paper, we will explain why the new SMP and MPP parallel solvers are fast from the perspective of the algorithms used. Additionally, we will attempt to clarify the influence of hardware system environments on SMP and MPP. This document can be thought of as pointers and precautions for hardware selection and software operation.

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