Leveraging JMAG-RT and FEA-based Models for High Fidelity Real-Time Test in FPGA

Ben Black
National Instruments

Abstract

Real-time test in the area of power electronics provides unique challenges that are difficult to address with traditional hardware-in-the-loop (HIL) systems. The high speed discrete switching states of power electronics systems mean that the simulation system needs to run on the order of 1 us to provide useful numerical results, and the benefits during algorithm development are directly related to the fidelity of the model. A good test system allows a control engineer to speed up the design cycle by allowing control testing to start without physical hardware, to test novel control algorithms without endangering hardware and to see potentially un-measureable parameters within the system. To address these issues and to provide a platform for HIL testing of electric motor systems, National Instruments has partnered with JSOL Corporation and developed field programmable gate array (FPGA) models that use JMAG-RT as a means to deploy the high-fidelity of an FEA simulation into the high speed of a FPGA processing node.

To read Proceedings, please sign-in.

Protected content here, for members only.
You need to sign in as a Regular JMAG Software User (paid user) or JMAG WEB MEMBER (free membership).

By registering as a JMAG WEB MEMBER, you can browse technical materials and other member-only contents for free.
If you are not registered, click the “Create an Account” button.

Create an Account Sign in 

Remember me
Sign In
Create an account (Free) About authentication ID for JMAG website

Search Filter

  • All Categories

Proceedings Archives